65 nanometer(nm) process technology

Intel President Paul Otellini introduces their 300mm wafer of silicon using 65 nanometer (nm) process technology during the Intel Autumn Communication Technology Summit in San Francisco, United States, Sept. 7, 2004. Intel, the world's largest chip maker, said recently that it has built fully functional 70-megabit static random access memory (SRAM) chips with more than half a billion transistors using 65 nanometer(nm) process technology.

Intel President Paul Otellini introduces their 300mm wafer of silicon using 65 nanometer (nm) process technology during the Intel Autumn Communication Technology Summit in San Francisco, United States, Sept. 7, 2004. Intel, the world's largest chip maker, said recently that it has built fully functional 70-megabit static random access memory (SRAM) chips with more than half a billion transistors using 65 nanometer(nm) process technology.